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-rw-r--r--Makefile4
-rw-r--r--board/glofiish/Makefile64
-rw-r--r--board/glofiish/config.mk32
-rw-r--r--board/glofiish/glofiish.c280
-rw-r--r--board/glofiish/jbt6k74.c430
-rw-r--r--board/glofiish/jbt6k74.h14
-rw-r--r--board/glofiish/lowlevel_foo.S109
-rw-r--r--board/glofiish/lowlevel_foo.lds56
-rw-r--r--board/glofiish/lowlevel_init.S169
-rw-r--r--board/glofiish/nand.c47
-rw-r--r--board/glofiish/u-boot.lds58
-rw-r--r--board/glofiish/udc.c29
-rw-r--r--include/asm-arm/mach-types.h1
-rw-r--r--include/configs/glofiish_x800.h293
14 files changed, 1586 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index 51f269c..0307be7 100644
--- a/Makefile
+++ b/Makefile
@@ -2431,6 +2431,10 @@ omap730p2_cs3boot_config : unconfig
sbc2410x_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
+glofiish_x800_config \
+glofiish_m800_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t glofiish NULL s3c24x0
+
gta02_config \
gta02v1_config \
gta02v2_config \
diff --git a/board/glofiish/Makefile b/board/glofiish/Makefile
new file mode 100644
index 0000000..49dea76
--- a/dev/null
+++ b/board/glofiish/Makefile
@@ -0,0 +1,64 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := glofiish.o nand.o jbt6k74.o udc.o
+SOBJS := lowlevel_init.o
+
+.PHONY: all
+
+all: $(LIB) lowevel_foo.bin
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+lowlevel_foo.o: lowlevel_foo.S
+ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4t \
+ -o lowlevel_foo.o lowlevel_foo.S
+
+lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds
+ $(LD) -T lowlevel_foo.lds -Ttext 0x00000000 -Bstatic \
+ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
+
+lowevel_foo.bin: lowlevel_foo
+ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
+ lowlevel_foo lowlevel_foo.bin
+
+
+clean:
+ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/glofiish/config.mk b/board/glofiish/config.mk
new file mode 100644
index 0000000..8e6af79
--- a/dev/null
+++ b/board/glofiish/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+# GTA01v3 has 1 bank of 64 MB SDRAM
+# GTA01v4 has 1 bank of 64 MB SDRAM
+#
+# 3000'0000 to 3400'0000
+# we load ourself to 33F8'0000
+#
+# GTA01Bv2 or later has 1 bank of 128 MB SDRAM
+#
+# 3000'0000 to 3800'0000
+# we load ourself to 37F8'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# download area is 3200'0000 or 3300'0000
+
+CONFIG_USB_DFU_VENDOR=0x1457
+CONFIG_USB_DFU_PRODUCT=0x5119
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0x33F80000
diff --git a/board/glofiish/glofiish.c b/board/glofiish/glofiish.c
new file mode 100644
index 0000000..4ca5a91
--- a/dev/null
+++ b/board/glofiish/glofiish.c
@@ -0,0 +1,280 @@
+/*
+ * (C) 2009 by Harald Welte <laforge@gnumonks.org>
+ *
+ * based on existing S3C2410 startup code in u-boot:
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2440.h>
+#include <i2c.h>
+#include <bootmenu.h>
+#include <asm/atomic.h>
+
+#include "jbt6k74.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define M_MDIV 42
+#define M_PDIV 1
+#define M_SDIV 0
+#define U_M_MDIV 88
+#define U_M_PDIV 4
+#define U_M_SDIV 2
+
+unsigned int neo1973_wakeup_cause;
+extern unsigned char booted_from_nand;
+extern int nobootdelay;
+extern int udc_usb_maxcurrent;
+
+char __cfg_prompt[20] = "X800 # ";
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+enum glofiish_led {
+ GFISH_LED_PWR_ORANGE = 0,
+ GFISH_LED_PWR_BLUE = 1,
+ GFISH_LED_AUX_RED = 2,
+};
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+static void cpu_speed(int mdiv, int pdiv, int sdiv, int clkdivn)
+{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+
+ /* clock divide */
+ clk_power->CLKDIVN = clkdivn;
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
+ /* configure MPLL */
+ clk_power->MPLLCON = ((mdiv << 12) + (pdiv << 4) + sdiv);
+
+ /* some delay between MPLL and UPLL */
+ delay (4000);
+
+ /* configure UPLL */
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (8000);
+}
+
+int board_init(void)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* FCLK = 200MHz values from cpu/arm920t/start.S */
+ cpu_speed(142, 7, 1, 3); /* 200MHZ, 1:2:4 */
+
+ *((u_int16_t *)0x08000018) = 1;
+ *((u_int16_t *)0x08000012) = 2;
+ *((u_int16_t *)0x08000010) = 3;
+
+ /* set up the I/O ports (from: booter on X800) */
+ gpio->GPACON = 0x005E16B1;
+ gpio->GPADAT = 0x00000B42;
+
+ //gpio->GPBCON = 0x00015155;
+ gpio->GPBCON = 0x0155555;
+ gpio->GPBDAT = 0x00000410; /* B10: microSD/MMC power */
+ gpio->GPBUP = 0x0000FFFF;
+
+ gpio->GPCCON = 0x55555555;
+ gpio->GPCDAT = 0x00000000;
+ gpio->GPCUP = 0x0000FFFF;
+
+ gpio->GPDCON = 0x55415555;
+ gpio->GPDDAT = 0x00000000;
+ gpio->GPDUP = 0x0000FFFF;
+
+ gpio->GPECON = 0x056AA915;
+ gpio->GPEDAT = 0x00000000;
+ gpio->GPEUP = 0x0000FFFF;
+
+ gpio->GPFCON = 0x00000088;
+ gpio->GPFDAT = 0x00000000;
+ gpio->GPFUP = 0x0000FFFF;
+
+ gpio->GPGCON = 0x55041400;
+ gpio->GPGDAT = 0x00006200;
+ gpio->GPGUP = 0x0000FFFF;
+
+ gpio->GPHCON = 0x0014A1AA;
+ gpio->GPHDAT = 0x00000000;
+ gpio->GPHUP = 0x0000FFFF;
+
+ gpio->GPJCON = 0x01400000;
+ gpio->GPJDAT = 0x00000000;
+ gpio->GPJUP = 0xFFFF;
+
+ {
+ u_int16_t f;
+ u_int8_t b;
+
+#if 0
+ f = *((u_int16_t *)0x0800001c);
+ f &= 0x0f;
+ b = 0x0b020000 + f << 1;
+ *((u_int16_t *)0x08000004) = *b++;
+ *((u_int16_t *)0x08000000) = *b;
+#endif
+ *((u_int16_t *)0x0800001e) = 2;
+ }
+
+ /* arch number of X800-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_GLOFIISH_X800;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+static void cpu_idle(void)
+{
+ S3C24X0_INTERRUPT * const intr = S3C24X0_GetBase_INTERRUPT();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_CLOCK_POWER * const clk = S3C24X0_GetBase_CLOCK_POWER();
+ unsigned long flags;
+
+ /*
+ * We don't want to execute interrupts throughout all this, since
+ * u-boot's interrupt handling code isn't modular, and getting a "real"
+ * interrupt without clearing it in the interrupt handler would cause
+ * us to loop permanently.
+ */
+ local_irq_save(flags);
+
+ /* go idle */
+ clk->CLKCON |= 1 << 2;
+
+ /* we're safe now */
+ local_irq_restore(flags);
+}
+
+
+int board_late_init(void)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ uint8_t int1, int2;
+ char buf[32];
+ int menu_vote = 0; /* <= 0: no, > 0: yes */
+ int seconds = 0;
+ int enter_bootmenu;
+ char *env_stop_in_menu;
+
+ cpu_speed(M_MDIV, M_PDIV, M_SDIV, 5); /* 400MHZ, 1:4:8 */
+
+ /* FIXME: issue a short pulse with the vibrator */
+
+ jbt6k74_init();
+ jbt6k74_enter_state(JBT_STATE_NORMAL);
+ jbt6k74_display_onoff(1);
+ /* switch on the backlight */
+ glofiish_backlight(1);
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+u_int32_t get_board_rev(void)
+{
+ return 0x1000;
+}
+
+void neo1973_poweroff(void)
+{
+ printf("poweroff\n");
+ udc_disconnect();
+ /* FIXME: actual poweroff */
+ /* don't return to caller */
+ while (1) ;
+}
+
+void glofiish_backlight(int on)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ if (on)
+ gpio->GPBDAT |= 1;
+ else
+ gpio->GPBDAT &= ~1;
+}
+
+/* FIXME: shared */
+void glofiish_vibrator(int on)
+{
+ if (on)
+ *((u_int16_t *)0x08000014) |= (1 << 2);
+ else
+ *((u_int16_t *)0x08000014) &= ~(1 << 2);
+}
+
+void neo1973_gsm(int on)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ /* FIXME */
+}
+
+void neo1973_gps(int on)
+{
+ /* FIXME */
+}
+
+/* The sum of all part_size[]s must equal to or greater than the NAND size,
+ i.e., 0x10000000. */
+
+unsigned int dynpart_size[] = {
+ CFG_UBOOT_SIZE, CFG_ENV_SIZE, 0x800000, 0xa0000, 0x40000, 0x10000000, 0 };
+char *dynpart_names[] = {
+ "u-boot", "u-boot_env", "kernel", "splash", "factory", "rootfs", NULL };
+
+void glofiish_led(int led, int on)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ /* FIXME */
+}
diff --git a/board/glofiish/jbt6k74.c b/board/glofiish/jbt6k74.c
new file mode 100644
index 0000000..ac44edd
--- a/dev/null
+++ b/board/glofiish/jbt6k74.c
@@ -0,0 +1,430 @@
+/* u-boot driver for the tpo JBT6K74-AS LCM ASIC
+ *
+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * Copyright (C) 2009 by Harald Welte <laforge@gnumonks.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <spi.h>
+#include <video_fb.h>
+#include <asm/errno.h>
+#include <s3c2410.h>
+#include "jbt6k74.h"
+
+#if 0
+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
+#define DEBUGPC(x, args...) printf(x, ## args);
+#else
+#define DEBUGP(x, args...) do { } while (0)
+#define DEBUGPC(x, args...) do { } while (0)
+#endif
+
+
+enum jbt_register {
+ JBT_REG_SLEEP_IN = 0x10,
+ JBT_REG_SLEEP_OUT = 0x11,
+
+ JBT_REG_DISPLAY_OFF = 0x28,
+ JBT_REG_DISPLAY_ON = 0x29,
+
+ JBT_REG_RGB_FORMAT = 0x3a,
+ JBT_REG_QUAD_RATE = 0x3b,
+
+ JBT_REG_POWER_ON_OFF = 0xb0,
+ JBT_REG_BOOSTER_OP = 0xb1,
+ JBT_REG_BOOSTER_MODE = 0xb2,
+ JBT_REG_BOOSTER_FREQ = 0xb3,
+ JBT_REG_OPAMP_SYSCLK = 0xb4,
+ JBT_REG_VSC_VOLTAGE = 0xb5,
+ JBT_REG_VCOM_VOLTAGE = 0xb6,
+ JBT_REG_EXT_DISPL = 0xb7,
+ JBT_REG_OUTPUT_CONTROL = 0xb8,
+ JBT_REG_DCCLK_DCEV = 0xb9,
+ JBT_REG_DISPLAY_MODE1 = 0xba,
+ JBT_REG_DISPLAY_MODE2 = 0xbb,
+ JBT_REG_DISPLAY_MODE = 0xbc,
+ JBT_REG_ASW_SLEW = 0xbd,
+ JBT_REG_DUMMY_DISPLAY = 0xbe,
+ JBT_REG_DRIVE_SYSTEM = 0xbf,
+
+ JBT_REG_SLEEP_OUT_FR_A = 0xc0,
+ JBT_REG_SLEEP_OUT_FR_B = 0xc1,
+ JBT_REG_SLEEP_OUT_FR_C = 0xc2,
+ JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
+ JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
+ JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
+ JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
+
+ JBT_REG_GAMMA1_FINE_1 = 0xc7,
+ JBT_REG_GAMMA1_FINE_2 = 0xc8,
+ JBT_REG_GAMMA1_INCLINATION = 0xc9,
+ JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
+
+ JBT_REG_BLANK_CONTROL = 0xcf,
+ JBT_REG_BLANK_TH_TV = 0xd0,
+ JBT_REG_CKV_ON_OFF = 0xd1,
+ JBT_REG_CKV_1_2 = 0xd2,
+ JBT_REG_OEV_TIMING = 0xd3,
+ JBT_REG_ASW_TIMING_1 = 0xd4,
+ JBT_REG_ASW_TIMING_2 = 0xd5,
+
+ JBT_REG_HCLOCK_VGA = 0xec,
+ JBT_REG_HCLOCK_QVGA = 0xed,
+
+};
+
+static const char *jbt_state_names[] = {
+ [JBT_STATE_DEEP_STANDBY] = "deep-standby",
+ [JBT_STATE_SLEEP] = "sleep",
+ [JBT_STATE_NORMAL] = "normal",
+};
+
+/* FIXME: glofish definitions */
+
+#define GTA01_SCLK (1 << 9) /* GPB9 */
+#define GTA01_MOSI (1 << 7) /* GPB7 */
+//#define GTA01_MISO (1 << 5) /* GPG5 */
+#define GTA01_CS (1 << 7) /* GPC7 */
+
+//#define SPI_READ ((immr->GPGDAT & GTA01_MISO) != 0)
+
+#define SPI_CS(bit) if (bit) gpio->GPCDAT |= GTA01_CS; \
+ else gpio->GPCDAT &= ~GTA01_CS
+
+#define SPI_SDA(bit) if (bit) gpio->GPBDAT |= GTA01_MOSI; \
+ else gpio->GPBDAT &= ~GTA01_MOSI
+
+#define SPI_SCL(bit) if (bit) gpio->GPBDAT |= GTA01_SCLK; \
+ else gpio->GPBDAT &= ~GTA01_SCLK
+
+/* 150uS minimum clock cycle, we have two of this plus our other
+ * instructions */
+#define SPI_DELAY udelay(100) /* 200uS */
+
+
+#define JBT_TX_BUF_SIZE
+struct jbt_info {
+ enum jbt_state state;
+ u_int16_t tx_buf[4];
+ struct spi_device *spi_dev;
+};
+
+static struct jbt_info _jbt, *jbt = &_jbt;
+
+static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ u_int16_t tmpdout = 0;
+ int i, j;
+
+ DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n",
+ *(uint *)dout, wordnum, bitlen);
+
+ SPI_CS(0);
+
+ for (i = 0; i < wordnum; i ++) {
+ tmpdout = dout[i];
+
+ for (j = 0; j < bitlen; j++) {
+ SPI_SCL(0);
+ if (tmpdout & (1 << bitlen-1)) {
+ SPI_SDA(1);
+ DEBUGPC("1");
+ } else {
+ SPI_SDA(0);
+ DEBUGPC("0");
+ }
+ SPI_DELAY;
+ SPI_SCL(1);
+ SPI_DELAY;
+ tmpdout <<= 1;
+ }
+ DEBUGPC(" ");
+ }
+ DEBUGPC("\n");
+
+ SPI_CS(1);
+
+ return 0;
+}
+
+#define JBT_COMMAND 0x000
+#define JBT_DATA 0x100
+
+static int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg)
+{
+ int rc;
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+
+ rc = jbt_spi_xfer(1, 9, jbt->tx_buf);
+
+ return rc;
+}
+
+
+static int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data)
+{
+ int rc;
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+ jbt->tx_buf[1] = JBT_DATA | data;
+
+ rc = jbt_spi_xfer(2, 9, jbt->tx_buf);
+
+ return rc;
+}
+
+static int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data)
+{
+ int rc;
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+ jbt->tx_buf[1] = JBT_DATA | (data >> 8);
+ jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
+
+ rc = jbt_spi_xfer(3, 9, jbt->tx_buf);
+
+ return rc;
+}
+
+static int jbt_init_regs(struct jbt_info *jbt)
+{
+ int rc;
+
+ DEBUGP("entering\n");
+
+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
+ rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
+ rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
+ rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
+ rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
+ rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
+ rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
+ /*
+ * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
+ * to avoid red / blue flicker
+ */
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
+ rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
+ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
+ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
+ rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
+
+#if 0
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+#endif
+
+ return rc;
+}
+
+static int standby_to_sleep(struct jbt_info *jbt)
+{
+ int rc;
+
+ DEBUGP("entering\n");
+
+ /* three times command zero */
+ rc = jbt_reg_write_nodata(jbt, 0x00);
+ udelay(1000);
+ rc = jbt_reg_write_nodata(jbt, 0x00);
+ udelay(1000);
+ rc = jbt_reg_write_nodata(jbt, 0x00);
+ udelay(1000);
+
+ /* deep standby out */
+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
+
+ return rc;
+}
+
+static int sleep_to_normal(struct jbt_info *jbt)
+{
+ int rc;
+ DEBUGP("entering\n");
+
+ /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
+
+ /* Quad mode off */
+ rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
+
+ /* AVDD on, XVDD on */
+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
+
+ /* Output control */
+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
+
+ /* Sleep mode off */
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
+
+ /* at this point we have like 50% grey */
+
+ /* initialize register set */
+ rc |= jbt_init_regs(jbt);
+ return rc;
+}
+
+static int normal_to_sleep(struct jbt_info *jbt)
+{
+ int rc;
+ DEBUGP("entering\n");
+
+ rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
+
+ return rc;
+}
+
+static int sleep_to_standby(struct jbt_info *jbt)
+{
+ DEBUGP("entering\n");
+ return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
+}
+
+/* frontend function */
+int jbt6k74_enter_state(enum jbt_state new_state)
+{
+ int rc = -EINVAL;
+
+ DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state);
+
+ switch (jbt->state) {
+ case JBT_STATE_DEEP_STANDBY:
+ switch (new_state) {
+ case JBT_STATE_DEEP_STANDBY:
+ rc = 0;
+ break;
+ case JBT_STATE_SLEEP:
+ rc = standby_to_sleep(jbt);
+ break;
+ case JBT_STATE_NORMAL:
+ /* first transition into sleep */
+ rc = standby_to_sleep(jbt);
+ /* then transition into normal */
+ rc |= sleep_to_normal(jbt);
+ break;
+ }
+ break;
+ case JBT_STATE_SLEEP:
+ switch (new_state) {
+ case JBT_STATE_SLEEP:
+ rc = 0;
+ break;
+ case JBT_STATE_DEEP_STANDBY:
+ rc = sleep_to_standby(jbt);
+ break;
+ case JBT_STATE_NORMAL:
+ rc = sleep_to_normal(jbt);
+ break;
+ }
+ break;
+ case JBT_STATE_NORMAL:
+ switch (new_state) {
+ case JBT_STATE_NORMAL:
+ rc = 0;
+ break;
+ case JBT_STATE_DEEP_STANDBY:
+ /* first transition into sleep */
+ rc = normal_to_sleep(jbt);
+ /* then transition into deep standby */
+ rc |= sleep_to_standby(jbt);
+ break;
+ case JBT_STATE_SLEEP:
+ rc = normal_to_sleep(jbt);
+ break;
+ }
+ break;
+ }
+
+ return rc;
+}
+
+int jbt6k74_display_onoff(int on)
+{
+ DEBUGP("entering\n");
+ if (on)
+ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
+ else
+ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+}
+
+int jbt6k74_init(void)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* initialize SPI for GPIO bitbang */
+ /* FIXME: glofiish */
+ gpio->GPGCON &= 0xffff033f;
+ gpio->GPGCON |= 0x00005440;
+
+ /* get LCM out of reset */
+ gpio->GPCDAT |= (1 << 6);
+
+ /* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms
+ * seems unreliable with later LCM batches, increasing to 90ms */
+ udelay(90000);
+
+ return 0;
+}
+
+void board_video_init(GraphicDevice *pGD)
+{
+ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+
+ lcd->LCDCON1 = 0x00000178; /* CLKVAL=1, BPPMODE=16bpp, TFT, ENVID=0 */
+
+ lcd->LCDCON2 = 0x019fc3c1;
+ lcd->LCDCON3 = 0x0039df67;
+ lcd->LCDCON4 = 0x00000007;
+ lcd->LCDCON5 = 0x0001cf09;
+ lcd->LPCSEL = 0x00000000;
+}
diff --git a/board/glofiish/jbt6k74.h b/board/glofiish/jbt6k74.h
new file mode 100644
index 0000000..cc20566
--- a/dev/null
+++ b/board/glofiish/jbt6k74.h
@@ -0,0 +1,14 @@
+#ifndef _JBT6K74_H
+#define _JBT6K74_H
+
+enum jbt_state {
+ JBT_STATE_DEEP_STANDBY,
+ JBT_STATE_SLEEP,
+ JBT_STATE_NORMAL,
+};
+
+int jbt6k74_init(void);
+int jbt6k74_display_onoff(int on);
+int jbt6k74_enter_state(enum jbt_state new_state);
+
+#endif
diff --git a/board/glofiish/lowlevel_foo.S b/board/glofiish/lowlevel_foo.S
new file mode 100644
index 0000000..fa2f3f8
--- a/dev/null
+++ b/board/glofiish/lowlevel_foo.S
@@ -0,0 +1,109 @@
+
+_start:
+ b reset
+undefvec:
+ b undefvec
+swivec:
+ b swivec
+pabtvec:
+ b pabtvec
+dabtvec:
+ b dabtvec
+rsvdvec:
+ b rsvdvec
+irqvec:
+ b irqvec
+fiqvec:
+ b fiqvec
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+/* turn off the watchdog */
+#define pWTCON 0x53000000
+#define LOCKTIME 0x4C000000
+#define IRQ_BASE 0x4A000000
+#define SRCPND 0x00
+#define INTMSK 0x08
+#define INTPND 0x10
+#define INTSUBMSK 0x1C
+
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+
+ mov r1, #0xffffffff
+ ldr r0, =IRQ_BASE
+ str r1, [r0,#INTMSK]
+ ldr r1, =0x3ff
+ str r1, [r0,#INTSUBMSK]
+
+ /* clear any pending interrupts. This can only happen in case
+ * we do something like soft_reset_halt in OpenOCD, resulting
+ * in only the CPU core being reset, not the peripherals */
+ ldr r1, [r0,#SRCPND]
+ str r1, [r0,#SRCPND]
+ ldr r1, [r0,#INTPND]
+ str r1, [r0,#INTPND]
+
+#if 0
+ /* configure PLL */
+ mov r0, #LOCKTIME
+
+ /* FCLK:HCLK:PCLK = 1:4:8 (500:125:62.5)*/
+ mov r1, #5
+ str r1, [r0,#14] /* CLKDIVN */
+
+ mov r1, #0xffffff
+ str r1, [r0]
+ ldr r1, =0x3C042 /* 48MHz */
+ str r1, [r0,#8] /* UPLLCON */
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ ldr r1, =0x6e021 /* 500MHz */
+ str r1, [r0,#4] /* MPLLCON */
+#endif
+
+ bl cpu_init_crit
+ ldr r0,=TEXT_BASE
+ mov pc, r0
+
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a lowlevel_init.S in your board directory.
+ */
+ mov ip, lr
+ bl lowlevel_init
+ mov lr, ip
+ mov pc, lr
+
diff --git a/board/glofiish/lowlevel_foo.lds b/board/glofiish/lowlevel_foo.lds
new file mode 100644
index 0000000..d320446
--- a/dev/null
+++ b/board/glofiish/lowlevel_foo.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ lowlevel_foo.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/glofiish/lowlevel_init.S b/board/glofiish/lowlevel_init.S
new file mode 100644
index 0000000..24bd1e1
--- a/dev/null
+++ b/board/glofiish/lowlevel_init.S
@@ -0,0 +1,169 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the E-TEN glofiish X800 by Harald Welte <laforge@gnumonks.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW16)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x3 /* 4clk */
+#define B1_Tcos 0x3 /* 4clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x3 /* 4clk */
+#define B1_Tah 0x3 /* 4clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x0 /* 0clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x0 /* 0clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x0 /* 0clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1 /* 3clk */
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* ?clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+//#define REFCNT 1011
+#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ adr r0, SMRDATA
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* setup asynchronous bus mode */
+ mrc p15, 0, r1 ,c1 ,c0, 0
+ orr r1, r1, #0xc0000000
+ mcr p15, 0, r1, c1, c0, 0
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32
+ .word 0x30
+ .word 0x30
diff --git a/board/glofiish/nand.c b/board/glofiish/nand.c
new file mode 100644
index 0000000..0078f35
--- a/dev/null
+++ b/board/glofiish/nand.c
@@ -0,0 +1,47 @@
+/*
+ * nand.c - Board-specific NAND setup
+ *
+ * Copyright (C) 2007 by OpenMoko, Inc.
+ * Written by Werner Almesberger <werner@openmoko.org>
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h" /* nand.h needs NAND_MAX_CHIPS */
+#include "linux/mtd/mtd.h"
+#include "linux/mtd/nand.h"
+#include "s3c2440.h"
+
+
+/* Derived from drivers/nand/nand_bbt.c:largepage_flashbased */
+
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr badblock_pattern = {
+ .options = NAND_BBT_SCAN2NDPAGE,
+ .offs = 0,
+ .len = 1,
+ .pattern = scan_ff_pattern
+};
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->badblock_pattern = &badblock_pattern;
+ return __board_nand_init(nand);
+}
diff --git a/board/glofiish/u-boot.lds b/board/glofiish/u-boot.lds
new file mode 100644
index 0000000..ba396ff
--- a/dev/null
+++ b/board/glofiish/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ cpu/arm920t/s3c24x0/nand_read.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) }
+ _end = .;
+}
diff --git a/board/glofiish/udc.c b/board/glofiish/udc.c
new file mode 100644
index 0000000..557c45c
--- a/dev/null
+++ b/board/glofiish/udc.c
@@ -0,0 +1,29 @@
+
+#include <common.h>
+#include <usbdcore.h>
+#include <s3c2410.h>
+
+int udc_usb_maxcurrent = 0;
+
+void udc_ctrl(enum usbd_event event, int param)
+{
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ switch (event) {
+ case UDC_CTRL_PULLUP_ENABLE:
+ if (param)
+ gpio->GPADAT |= (1 << 21); /* GPA21 */
+ else
+ gpio->GPADAT &= ~(1 <<21);
+ break;
+ case UDC_CTRL_500mA_ENABLE:
+ /* FIXME */
+ if (param)
+ udc_usb_maxcurrent = 500;
+ else
+ udc_usb_maxcurrent = 0;
+ break;
+ default:
+ break;
+ }
+}
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index aaf2ea2..ea26f91 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_P300 1602
#define MACH_TYPE_XDACOMET 1603
#define MACH_TYPE_DEXFLEX2 1604
+#define MACH_TYPE_GLOFIISH_X800 1772
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
diff --git a/include/configs/glofiish_x800.h b/include/configs/glofiish_x800.h
new file mode 100644
index 0000000..14641e6
--- a/dev/null
+++ b/include/configs/glofiish_x800.h
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ * Configuation settings for the FIC Neo1973 GTA02 Linux GSM phone
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* we want to be able to start u-boot directly from within NAND flash */
+#define CONFIG_LL_INIT_NAND_ONLY
+#define CONFIG_S3C2410_NAND_BOOT 1
+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
+
+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 16934400/* the X800 has this input clock */
+
+
+#define USE_920T_MMU 1
+#define CONFIG_USE_IRQ 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024)
+ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3 1
+#define CONFIG_SERIAL_MULTI
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_ENV
+ /* CFG_CMD_IRQ | */ \
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+ /* CFG_CMD_BMP | */ \
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+//#define CONFIG_CMD_DATE
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MISC
+ /* CFG_CMD_USB | */ \
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DIAG
+ /* CFG_CMD_HWFLOW | */ \
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_LICENSE
+#define CONFIG_CMD_TERMINAL
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS ""
+#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
+
+#define CONFIG_DOS_PARTITION 1
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+
+#define STRINGIFY(s) DO_STRINGIFY(s) /* expand the argument */
+#define DO_STRINGIFY(s) #s /* quote it */
+#define CFG_PROMPT "X800 # "
+ /* Monitor Command Prompt */
+#define CONFIG_S3C2442 1 /* SAMSUNG S3C2442 SoC */
+
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 64 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CFG_HZ 1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_BOOTMENU
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+#if 0
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x49000000 /* S3C24X0_USB_HOST_BASE */
+#define CFG_USB_OHCI_SLOT_NAME "s3c2440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+#endif
+
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+#define CONFIG_USBD_VENDORID 0x1d50 /* OpenMoko, Inc. */
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
+#define CONFIG_USBD_MANUFACTURER "GNUfiish"
+#define CONFIG_USBD_PRODUCT_NAME "X800 Bootloader " U_BOOT_VERSION
+#define CONFIG_USBD_DFU 1
+#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
+#define CONFIG_USBD_DFU_INTERFACE 2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0" \
+ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock6 console=ttySAC2,115200 console=tty0 loglevel=8\0" \
+ ""
+
+ //"stderr=usbtty\0stdout=usbtty\0stdin=usbtty\0"
+
+#define CONFIG_CMD_LOADENV
+#define CONFIG_CMD_DEFAULTENV
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_NO_FLASH 1
+
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_SIZE 0x40000 /* 128k Total Size of Environment Sector */
+#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
+#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
+#define CFG_ENV_OVERRIDE /* allow pre-loading the environment */
+
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE 0x4e000000
+#define CFG_MAX_NAND_DEVICE 1
+
+#define CONFIG_MMC 1
+#define CONFIG_MMC_WIDE 1
+#define CONFIG_MMC_S3C 1
+#define CFG_MMC_BASE 0xff000000
+
+/* EXT2 driver */
+#define CONFIG_EXT2 1
+
+#define CONFIG_FAT 1
+#define CONFIG_SUPPORT_VFAT
+
+#if 1
+/* JFFS2 driver */
+#define CONFIG_JFFS2_CMDLINE 1
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_NAND_DEV 0
+//#define CONFIG_JFFS2_NAND_OFF 0x634000
+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
+#endif
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_REVISION_TAG 1
+#if 0
+#define CONFIG_SERIAL_TAG 1
+#endif
+
+#define CONFIG_DRIVER_S3C24X0_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50633 data sheet */
+#define CFG_I2C_SLAVE 0x7f
+
+/* we have a board_late_init() function */
+#define BOARD_LATE_INIT 1
+
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_S3C2410
+#define CONFIG_CFB_CONSOLE
+//#define CONFIG_VIDEO_LOGO
+//#define CONFIG_SPLASH_SCREEN
+#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CMD_UNZIP
+
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+
+#define VIDEO_KBD_INIT_FCT 0
+#define VIDEO_TSTC_FCT serial_tstc
+#define VIDEO_GETC_FCT serial_getc
+
+#define LCD_VIDEO_ADDR 0x33d00000
+#endif
+
+#define CONFIG_S3C2410_NAND_BBT 1
+//#define CONFIG_S3C2410_NAND_HWECC 1
+
+#define MTDIDS_DEFAULT "nand0=glofiish-nand"
+//#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),128k(u-boot_env),8M(kernel),640k(splash),256k(factory),-(rootfs)"
+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "glofiish-nand"
+#define CONFIG_NAND_DYNPART
+
+#define DFU_NUM_ALTERNATES 7
+
+#ifndef __ASSEMBLY__
+extern int gta02_revision; /* use this instead of CONFIG_GTA02_REVISION */
+#endif
+
+#define CONFIG_USB_DFU_REVISION 0x0010
+
+#endif /* __CONFIG_H */
generated by cgit v0.9-8-g568d at 2013-05-19 18:51:31 (GMT)